1. Technical Field
The present disclosure relates to a MOS transistor and to a MOS transistor manufacturing method.
2. Description of the Related Art
In the field of microelectronic components, it is constantly attempted to improve MOS transistor performances and to increase their integration density in integrated circuit chips. It is especially desired to increase the on-state current and to decrease leakage currents of MOS transistors while decreasing the size thereof.
As MOS transistors miniaturize and their gate length decreases, new effects appear, which especially result in an increase of leakage currents. To attenuate such effects, the doping levels, as well as the thickness and the nature of the gate insulator have had to be adapted, for example, by using a material of higher dielectric permittivity than silicon oxide. However, this uses complex and unreliable techniques.
New MOS transistor structures have also been provided. Among these, MOS transistors formed in SOI-type silicon on-insulator layers sufficiently thin for the gate to act across the entire silicon layer thickness when it is activated have been provided. Such structures are currently called FDSOI (“Fully Depleted Silicon-On-Insulator”) in the art. So-called fin structures have also been provided. Such structures provide a better electrostatic control of the channel by the gate. However, they generally have the disadvantage of introducing stray capacitances of non-negligible value as compared with the on-state capacitance between the MOS transistor gate and channel. This causes a decrease of the on-state-to-off-state and back switching speed of the MOS transistor.